1. Field
Embodiments of the present disclosure relate to a memory device and a memory system including the same, and more particularly, to a memory device supporting rank-level parallelism and a memory system including the same.
2. Description of the Related Art
A memory system using a Dynamic Random Access Memory (DRAM) has a hierarchical structure including a plurality of channels. For example, a channel includes a plurality of ranks, and a rank includes a plurality of banks.
FIG. 1 illustrates a conventional memory system 1.
The conventional memory system 1 includes a memory controller 60 and a plurality of ranks 10 to 40 coupled to the memory controller 60.
The memory controller 60 and the plurality of ranks 10 to 40 are coupled to each other through a rank shared bus 50. The rank shared bus 50 may be referred to as a channel.
In FIG. 1, the conventional memory system 1 includes four ranks, that is, a first rank 10, a second rank 20, a third rank 30, and a fourth rank 40.
The first rank 10 includes a first plurality of banks 11 to 18, which are first to eighth banks 11 to 18.
The first plurality of banks 11 to 18 share a first rank bus 19, and the first rank bus 19 is coupled to the rank shared bus 50.
The second rank 20 includes a second plurality of banks 21 to 28, which are first to eighth banks 21 to 28 and share a second rank bus 29, and the second rank bus 29 is coupled to the rank shared bus 50.
The third rank 30 includes a third plurality of banks 31 to 38, which are first to eighth banks 31 to 38 and share a third rank bus 39, and the third rank bus 39 is coupled to the rank shared bus 50.
The fourth rank 40 includes a fourth plurality of banks 41 to 48, which are first to eighth banks 41 to 48 and share a fourth rank bus 49, and the fourth rank bus 49 is coupled to the rank shared bus 50.
In the conventional memory system 1, each of the banks 11 to 18, 21 to 28, 31 to 38, and 41 to 48 includes a row buffer. Based on such a configuration, the conventional memory system 1 supports bank-level parallelism for performing an operation on one of the banks 11 to 18, 21 to 28, 31 to 38, and 41 to 48 while performing an operation on another one of the banks 11 to 18, 21 to 28, 31 to 38, and 41 to 48.
In the conventional memory system 1, however, the first, second, third, and fourth ranks 10, 20, 30, and 40 are coupled to the memory controller 60 in common through the rank shared bus 50.
Thus, when one of the ranks 10, 20, 30, and 40 uses the rank shared bus 50, another one of the ranks 10, 20, 30, and 40 cannot use the rank shared bus 50.
When a row access operation such as an active operation or a precharge operation in a DRAM is performed at a bank level, a row buffer of a corresponding bank is used. Using different row buffers, different banks can perform respective row access operations at the same time. For example, in the conventional memory system 1 shown in FIG. 1, when the first bank 31 of the third rank 30 performs an active operation, the eighth bank 38 of the third rank 30 can perform a precharge operation at the same time.
When a column access operation such as a read operation or a write operation is performed, however, a row buffer and a memory controller transmit and receive data therebetween through a corresponding rank bus and a rank shared bus. Thus, in order to prevent a data collision, the column access operation must be performed only on one rank at a time. For example, in the conventional memory system 1 shown in FIG. 1, when a read operation is performed on the first rank 10, a write operation cannot be performed on the fourth rank 40 at the same time.
Thus, when the plurality of ranks 10, 20, 30, and 40 read column data, the ranks 10, 20, 30, and 40 sequentially read the data. Therefore, the performance of the conventional memory system 1 may be degraded by a time delay.